High-Frequency Trading Architecture: Kernel Bypass (Solarflare OpenOnload), FPGA, and Sub-Microsecond Execution

#include <onload/onload.h>
#include <stdio.h>
#include <stdlib.h>

#define RX_RING_SIZE 4096
#define PKT_BUF_SIZE 2048

int main(void) {
    ef_driver_handle drv;
    ef_vi vi;
    ef_vi_rx_desc rx_desc[RX_RING_SIZE];
    char *pkt_buf[RX_RING_SIZE];
    int i, rc;

    /* Initialise driver & VI */
    ef_driver_open(&drv, NULL);
    ef_vi_alloc_from_driver(&vi, &drv, 0, 0, RX_RING_SIZE, 0, NULL);
    ef_vi_receive_post(&vi, rx_desc, RX_RING_SIZE);

    /* Pre‑register buffers */
    for (i = 0; i < RX_RING_SIZE; ++i) {
        pkt_buf[i] = malloc(PKT_BUF_SIZE);
        ef_vi_receive_post_buf(&vi, pkt_buf[i], PKT_BUF_SIZE);
    }

    /* Poll loop */
    while (1) {
        ef_event ev;
        while (ef_event_queue_poll(&vi, &ev, 1) == 1) {
            if (EF_EVENT_TYPE(ev) == EF_EVENT_TYPE_RX) {
                int ix = EF_EVENT_RX_DESC_ID(ev);
                /* Process packet in pkt_buf[ix] */
                // ... decode market data ...
                ef_vi_receive_post_buf(&vi, pkt_buf[ix], PKT_BUF_SIZE);
            }
        }
    }
}

ef_event_queue_poll

pkt_buf[ix]

copy_to_user

skb

#include <rte_eal.h>
#include <rte_ethdev.h>
#include <rte_mbuf.h>

#define NB_RX_DESC 1024
#define BURST_SIZE 32

int main(int argc, char **argv) {
    struct rte_mempool *mbuf_pool;
    uint16_t port_id = 0;
    struct rte_mbuf *pkts[BURST_SIZE];
    int i, nb_rx;

    /* EAL init (hugepages, VFIO) */
    rte_eal_init(argc, argv);
    mbuf_pool = rte_pktmbuf_pool_create("MBUF_POOL",
                                        8192, 256, 0,
                                        RTE_MBUF_DEFAULT_BUF_SIZE,
                                        rte_socket_id());

    /* Port configuration */
    struct rte_eth_conf port_conf = {0};
    rte_eth_dev_configure(port_id, 1, 1, &port_conf);
    rte_eth_rx_queue_setup(port_id, 0, NB_RX_DESC,
                           rte_socket_id(), NULL, mbuf_pool);
    rte_eth_tx_queue_setup(port_id, 0, NB_RX_DESC,
                           rte_socket_id(), NULL);
    rte_eth_dev_start(port_id);

    /* Main poll loop */
    while (1) {
        nb_rx = rte_eth_rx_burst(port_id, 0, pkts, BURST_SIZE);
        for (i = 0; i < nb_rx; ++i) {
            struct rte_mbuf *m = pkts[i];
            // Process market data directly from m->buf_addr
            // ...
            rte_pktmbuf_free(m);
        }
    }
}

#include <net/netmap_user.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>

#define IFNAME "eth0"
#define BATCH  64

int main(void) {
    struct nm_desc *d = nm_open(IFNAME, NULL, 0, NULL);
    if (!d) { perror("nm_open"); exit(1); }

    while (1) {
        struct pollfd pfd = { .fd = d->fd, .events = POLLIN };
        poll(&pfd, 1, -1);   // block until packets arrive

        uint32_t cur = d->rx_ring->cur;
        uint32_t lim = d->rx_ring->head;
        while (cur != lim) {
            struct netmap_slot *slot = &d->rx_ring->slot[cur];
            char *pkt = NETMAP_BUF(d->rx_ring, slot->buf_idx);
            // Process pkt of length slot->len
            // ...
            cur = (cur + 1) % d->rx_ring->num_slots;
        }
        d->rx_ring->cur = cur;
    }
}

+-------------------+    PCIe Gen4 x16    +-------------------+
|  Host Memory      | <-----------------> |  FPGA (U280)      |
|  (RX Ring)        |   DMA (RX)          |  • Packet Parser  |
|  (TX Ring)        | <-----------------> |  • Risk Engine   |
+-------------------+    PCIe Gen4 x16    |  • Order Builder |
                                         +-------------------+

---

## Part 2 – Low‑Latency Primitives & Core Isolation  
*High‑Frequency Trading Architecture: Kernel Bypass (Solarflare OpenOnload), FPGA, and Sub‑Microsecond Execution*  

> **NOTE** – This section assumes you have already provisioned a bare‑metal server equipped with a Solarflare SFN7002/7012 NIC, an Intel Xeon Gold 6338 (or AMD EPYC 9654) and, optionally, a PCIe‑Gen4 FPGA accelerator (e.g. Xilinx U280). All kernel parameters referenced below are for a **2‑socket, 56‑core per socket** configuration, but the concepts translate verbatim to any modern x86‑64 platform.

---

## 4. Zero‑Allocation C++23 Patterns: Branchless Programming, Bitmasks, and `alignas(64)`

### 4.1 Why “Zero‑Allocation” Matters in HFT

| Metric | Typical Value (with allocation) | Zero‑allocation Target |
|--------|--------------------------------|------------------------|
| Latency per order (µs) | 3.4 – 5.2 | ≤ 1.2 |
| CPU cycles per packet | 12 k – 18 k | ≤ 5 k |
| Cache‑miss penalty (L3) | ~ 40 ns | < 5 ns (L1 hit) |

Every dynamic allocation incurs a *malloc*‑side‑effect: a lock, a possible page‑fault, and a **cache‑line bounce** across the memory hierarchy. In a sub‑microsecond pipeline we must **eliminate** any heap interaction after the NIC’s DMA has placed the packet into a pre‑registered user‑space buffer.

C++23 gives us three orthogonal tools to achieve this:

1. **`alignas(64)`** – Guarantees that a data structure starts on a cache‑line boundary, eliminating false sharing.
2. **Branchless bitmask tricks** – Convert control‑flow into arithmetic that the out‑of‑order engine can execute in parallel.
3. **`std::span` + `std::array` + `constexpr` bit‑fields** – Provide *view‑only* zero‑copy access with compile‑time layout guarantees.

Below is a **production‑grade market‑data parser** that demonstrates all three. The code is deliberately long (≈ 120 LOC) to expose realistic error handling, compile‑time validation, and inline documentation.

---  

### 4.2 Full Implementation – Zero‑Copy Market‑Data Decoder

```cpp
//=== market_decoder.hpp =====================================================
//  High‑frequency market‑data decoder – zero‑allocation, branchless, cache‑aligned
//  Target: Intel Xeon Gold 6338 / AMD EPYC 9654 (64‑byte cache line)
//  Requires: C++23, Linux, Solarflare OpenOnload (user‑space NIC buffers)
//============================================================================
#pragma once
#include <cstdint>
#include <cstddef>
#include <span>
#include <array>
#include <bit>
#include <system_error>
#include <cstring>
#include <immintrin.h>          // _mm_prefetch, _mm_loadu_si128
#include <unistd.h>             // ::sysconf
#include <sys/mman.h>           // ::mlock

// ---------------------------------------------------------------------------
// 1️⃣  Compile‑time constants & sanity checks
// ---------------------------------------------------------------------------
static constexpr std::size_t CACHE_LINE = 64;
static_assert(CACHE_LINE == ::sysconf(_SC_LEVEL1_DCACHE_LINESIZE),
              "Cache line size mismatch – adjust CACHE_LINE constant");

// ---------------------------------------------------------------------------
// 2️⃣  Bitmask utilities – constexpr, branchless
// ---------------------------------------------------------------------------
namespace mask {
    // Extract bits [hi:lo] from a 64‑bit word (inclusive)
    [[nodiscard]] constexpr std::uint64_t extract(std::uint64_t word,
                                                  unsigned lo,
                                                  unsigned hi) noexcept {
        const unsigned width = hi - lo + 1;
        const std::uint64_t mask = (std::uint64_t{1} << width) - 1;
        return (word >> lo) & mask;
    }

    // Sign‑extend a field of `bits` width, branchless
    [[nodiscard]] constexpr std::int64_t sign_extend(std::uint64_t value,
                                                     unsigned bits) noexcept {
        const std::int64_t shift = 64 - bits;
        return (static_cast<std::int64_t>(value) << shift) >> shift;
    }
}

// ---------------------------------------------------------------------------
// 3️⃣  Core data structures – cache‑line aligned
// ---------------------------------------------------------------------------
struct alignas(CACHE_LINE) OrderBookEntry {
    std::int64_t price;      // price * 10⁴ (fixed‑point)
    std::int32_t size;       // quantity
    std::uint16_t level;     // depth level
    std::uint8_t  side;      // 0 = bid, 1 = ask
    std::uint8_t  _pad[33];  // Pad to 64 B, reserve for future fields
};

static_assert(sizeof(OrderBookEntry) == CACHE_LINE,
              "OrderBookEntry must occupy exactly one cache line");

// ---------------------------------------------------------------------------
// 4️⃣  Message header – packed, no padding, branchless decode
// ---------------------------------------------------------------------------
struct [[gnu::packed]] MsgHeader {
    std::uint16_t msg_type;   // 0 = Trade, 1 = Quote, …
    std::uint16_t length;     // payload length in bytes (incl. header)
    std::uint32_t seq_no;     // monotonic sequence number
    std::uint64_t ts_ns;      // nanosecond‑resolution timestamp
};

// ---------------------------------------------------------------------------
// 5️⃣  Decoder class – owns a pre‑registered OpenOnload buffer slice
// ---------------------------------------------------------------------------
class alignas(CACHE_LINE) MarketDecoder {
public:
    // Constructor takes a raw pointer to a pre‑registered memory region.
    // The region must be page‑aligned, locked, and at least `capacity` bytes.
    MarketDecoder(void* region, std::size_t capacity) noexcept
        : buffer_{static_cast<std::byte*>(region), capacity}
    {
        // Prefault the region to guarantee it stays resident.
        ::mlock(region, capacity);
    }

    // -----------------------------------------------------------------------
    // 5.1  Public API – parse a single packet (zero copy)
    // -----------------------------------------------------------------------
    std::error_code parse_packet(std::size_t offset,
                                 OrderBookEntry& out) noexcept
    {
        // Bounds‑check – must stay within the buffer
        if (offset + sizeof(MsgHeader) > buffer_.size())
            return std::make_error_code(std::errc::invalid_argument);

        // Prefetch the header into L1 – non‑temporal hint to avoid polluting L1
        _mm_prefetch(reinterpret_cast<const char*>(buffer_.data() + offset),
                     _MM_HINT_T0);

        // 1️⃣ Load header (unaligned load – safe because OpenOnload guarantees
        //    64‑byte alignment for each packet)
        const MsgHeader* hdr = std::bit_cast<const MsgHeader*>(
            buffer_.data() + offset);

        // 2️⃣ Validate length – branchless check using a mask
        const std::uint16_t len = hdr->length;
        const bool len_ok = (len >= sizeof(MsgHeader)) &
                            (len <= max_payload_);
        if (!len_ok)
            return std::make_error_code(std::errc::protocol_error);

        // 3️⃣ Decode payload – assume a packed 64‑bit quote format:
        //    [63:48] price (signed, 16‑bit, scaled by 10⁴)
        //    [47:32] size  (unsigned 16‑bit)
        //    [31:16] level (unsigned 8‑bit) + side (8‑bit)
        //    [15:0]  reserved
        const std::uint64_t raw_payload =
            *std::bit_cast<const std::uint64_t*>(buffer_.data() + offset + sizeof(MsgHeader));

        // Branchless extraction
        const std::int64_t price_raw = mask::sign_extend(mask::extract(raw_payload, 48, 63), 16);
        const std::uint32_t size_raw = static_cast<std::uint32_t>(mask::extract(raw_payload, 32, 47));
        const std::uint16_t level_raw = static_cast<std::uint16_t>(mask::extract(raw_payload, 16, 23));
        const std::uint8_t  side_raw  = static_cast<std::uint8_t>(mask::extract(raw_payload, 24, 31));

        // 4️⃣ Populate the output structure – everything is already aligned.
        out.price = price_raw * 10'000;   // convert to fixed‑point
        out.size  = static_cast<std::int32_t>(size_raw);
        out.level = level_raw;
        out.side  = side_raw;

        // 5️⃣ Return success
        return {};
    }

    // -----------------------------------------------------------------------
    // 5.2  Helper – compute latency estimate (theoretical)
    // -----------------------------------------------------------------------
    static constexpr double theoretical_latency_ns(std::size_t bytes) noexcept {
        // L1 bandwidth ≈ 64 B per cycle @ 3.5 GHz → 0.018 ns/byte
        constexpr double ns_per_byte = 0.018;
        return bytes * ns_per_byte;
    }

private:
    std::span<std::byte> buffer_;
    static constexpr std::uint16_t max_payload_ = 256; // safety cap
};

+-------------------+-------------------+-------------------+-------------------+
| 64‑B Cache Line 0 | 64‑B Cache Line 1 | 64‑B Cache Line 2 | 64‑B Cache Line 3 |
+-------------------+-------------------+-------------------+-------------------+
| OrderBookEntry[0] | OrderBookEntry[1] | OrderBookEntry[2] | OrderBookEntry[3] |
| (price,size,…)    | (price,size,…)    | (price,size,…)    | (price,size,…)    |
+-------------------+-------------------+-------------------+-------------------+

OrderBookEntry

movnti

store

/etc/default/grub

GRUB_CMDLINE_LINUX_DEFAULT="quiet splash isolcpus=2-5,10-13 nosmt nohz_full=2-5,10-13 rcu_nocbs=2-5,10-13"

sudo update-grub && reboot

$ cat /proc/cmdline
... isolcpus=2-5,10-13 nosmt nohz_full=2-5,10-13 rcu_nocbs=2-5,10-13

//=== core_affinity.hpp ======================================================
//  Runtime CPU affinity utilities – zero‑allocation, error‑aware
//  Requires: glibc ≥ 2.31 (pthread_setaffinity_np), C++23
//============================================================================
#pragma once
#include <pthread.h>
#include <sched.h>
#include <system_error>
#include <charconv>
#include <array>
#include <string_view>
#include <span>
#include <bitset>
#include <iostream>

namespace affinity {

    // -----------------------------------------------------------------------
    // 1️⃣  Parse a CSV list of core IDs into a std::bitset<256>
    // -----------------------------------------------------------------------
    constexpr std::size_t MAX_CPUS = 256;
    using cpu_mask_t = std::bitset<MAX_CPUS>;

    [[nodiscard]] inline std::error_code parse_mask(std::string_view csv,
                                                    cpu_mask_t& out) noexcept
    {
        out.reset();
        std::size_t pos = 0;
        while (pos < csv.size()) {
            std::size_t next = csv.find(',', pos);
            std::string_view token = csv.substr(pos,
                               (next == std::string_view::npos) ? std::string_view::npos
                                                                : next - pos);
            unsigned core = 0;
            auto [ptr, ec] = std::from_chars(token.data(),
                                             token.data() + token.size(),
                                             core);
            if (ec != std::errc()) return std::make_error_code(std::errc::invalid_argument);
            if (core >= MAX_CPUS) return std::make_error_code(std::errc::result_out_of_range);
            out.set(core);
            if (next == std::string_view::npos) break;
            pos = next + 1;
        }
        return {};
    }

    // -----------------------------------------------------------------------
    // 2️⃣  Verify that a core belongs to the

---

## Part 3 – High‑Frequency Trading Architecture: Kernel Bypass (Solarflare OpenOnload), FPGA, and Sub‑Microsecond Execution  
### (Continuation – Sections 6 & 7 plus supplemental artefacts)

---

## 6. FSBL Telemetry Test: Kernel‑Socket vs. Kernel‑Bypass Round‑Trip Latency Histogram  

### 6.1 Test‑bed Overview  

| Component | Model / SKU | Quantity | Firmware / Driver | Notes |
|-----------|-------------|----------|-------------------|-------|
| **CPU** | AMD EPYC 9654 (8‑core @ 3.7 GHz, 128 MiB L3) | 2 sockets (16 cores total) | Linux 6.8, `amd64` microcode 0x30 | NUMA‑aware pinning, `isolcpus=2‑3,6‑7` |
| **NIC** | Solarflare X2522‑DP (25 GbE, OpenOnload 8.2.0) | 2 (active‑passive) | `sfboot` 4.3.2, `ethtool -K` offloads enabled | RSS‑hash 64‑bit, IRQ‑affinity to core 2 |
| **FPGA** | Xilinx Alveo U280 (HBM2 8 GB) | 1 | Vitis 2023.2, PCIe Gen4 x16 | Custom order‑book engine (see Part 2) |
| **GPU** | NVIDIA H100 80 GB SXM5 | 1 | CUDA 12.3, NVLink 2× | Used for AI‑driven quoting (off‑load) |
| **Storage** | Intel Optane PM 7302 (1.5 TB) RAID‑0 (NVMe) | 2 | `nvme-cli` 1.14 | Persistent telemetry logs |
| **OS** | Ubuntu 24.04 LTS (kernel 6.8.0‑1010‑generic) | – | `openonload` kernel module loaded, `sysctl -w net.core.somaxconn=65535` | Real‑time patches disabled (CFS‑RT not required for pure kernel‑bypass) |

All devices are **NUMA‑aligned**: the NIC, FPGA, and H100 sit on the same NUMA node (socket 0) to eliminate cross‑socket PCIe latency. The test harness runs on a dedicated “client” core (core 2) while the “server” logic (order‑book engine) is pinned to core 6. Clock synchronization between host and FPGA is performed via **PTP v2** (grandmaster on the NIC) with sub‑nanosecond stability (σ ≈ 0.28 ns).

### 6.2 Measurement Methodology  

The latency measurement code is a minimal **ping‑pong** using the *OpenOnload* API (`onload_socket`) and a plain POSIX socket for the baseline. Both paths share the same binary to eliminate binary‑size bias. The payload is a **64‑byte** market data packet (typical for a Level‑2 quote).  

```c
/* latency_test.c – compiled with -O3 -march=native */
#include <onload/socket.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <inttypes.h>

#define ITER 10'000'000
#define PAYLOAD_SZ 64

static inline uint64_t rdtsc(void) {
    unsigned hi, lo;
    __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
    return ((uint64_t)hi << 32) | lo;
}

int main(void) {
    int fd = socket(AF_INET, SOCK_DGRAM, 0);               // baseline
    int fd_ob = onload_socket(AF_INET, SOCK_DGRAM, 0);    // OpenOnload
    struct sockaddr_in srv = {.sin_family = AF_INET,
                              .sin_port   = htons(5000),
                              .sin_addr   = {.s_addr = htonl(INADDR_LOOPBACK)}};

    bind(fd, (struct sockaddr*)&srv, sizeof(srv));
    bind(fd_ob, (struct sockaddr*)&srv, sizeof(srv));

    char tx[PAYLOAD_SZ] = {0}, rx[PAYLOAD_SZ];
    uint64_t *latency = calloc(ITER, sizeof(uint64_t));
    if (!latency) abort();

    for (size_t i = 0; i < ITER; ++i) {
        uint64_t t0 = rdtsc();
        sendto(fd_ob, tx, PAYLOAD_SZ, 0, (struct sockaddr*)&srv, sizeof(srv));
        recvfrom(fd_ob, rx, PAYLOAD_SZ, 0, NULL, NULL);
        uint64_t t1 = rdtsc();
        latency[i] = t1 - t0;
    }

    /* Export raw TSC values for post‑processing */
    FILE *out = fopen("latency_ob.raw", "wb");
    fwrite(latency, sizeof(uint64_t), ITER, out);
    fclose(out);
    free(latency);
    return 0;
}

/proc/cpuinfo

cpu MHz

clock_gettime(CLOCK_MONOTONIC_RAW)

import numpy as np
import matplotlib.pyplot as plt

raw = np.fromfile('latency_ob.raw', dtype=np.uint64) * 1e9 / 2.68e9   # ns
bins = np.logspace(np.log10(50), np.log10(5000), num=50)   # 50 ns → 5 µs
hist, edges = np.histogram(raw, bins=bins)
plt.step(edges[:-1], hist, where='post')
plt.xscale('log')
plt.xlabel('Round‑trip latency (ns)')
plt.ylabel('Count')
plt.title('OpenOnload vs. Kernel Socket – 10 M iterations')
plt.grid(True, which='both')
plt.show()